Various reconfigurable logic devices, such as field programmable gate arrays (FPGA) are available commercially, from companies such as Xilinx, Actel, and Altera. However, such conventional reconfigurable devices are limited in terms of programmability or functionality for realizing different logic structures.
For example, designers may implement logic in large multiplexers as programmable logic fabric using a tree like structure, as shown conventionally in FIG. 1a. Such multiplexer size is an 8:1 MUX, having data inputs I0 through I7, and select lines S0 through S2. Because the prior-art tree structure requires that connections be increased at first level 118 to implement larger multiplexers, it is difficult to create larger multiplexers due to size and space considerations. Levels 119 and 120 represent inputs of what could be a larger multiplexer structure. By adding on additional levels, such as 118, it is apparent that the resulting multiplexer structure would grow in size with each added level.
Accordingly, an improved approach for reconfigurable logic design is required.